As of Jan 2016 I'm working on a new version of my Chirp beacon.

Over Christmas i taught myself the very basics of Verilog code using my Altera De0Nano FPGA development board, this has been sitting around for quite a few years now!
This entailed flashing an LED first :-) and then moved on to an Audio band pass filter using the on-board ADC and an R2R DAC output, then onto a mixer and extremely basic software receiver.. i will detail that somewhere on the site soon.

Anyway the new beacon is being based on the Red Pitaya FPGA/ARM CPU development board based on a Zynq chip which uses two ADC and DAC sampling at 125MHz enabling a software radio transceiver covering 50MHz.

The idea is to build some FPGA code to generate the Chirp signal at 50MHz with adjustable parameters and have it trigger on an external 1Hz input from my GPS receiver.
After this i will try(!) and build something to do the same for a synchronised Rx, trigger on the 1Hz signal and then record some filtered and down-converted samples from 50MHz into RAM.

There will be another program on the CPU to do the configuration and processing of the received samples, then maybe some web based display like other apps on the Red Pitaya... but that will be MUCH further down the line!

Here is the current block diagram of the Tx side, it uses some of the Xilinx IP and some made by Pavel who created the HPSDR code for the board.

Vivado Block

Current status 8/3/2016:
I have the basics of the Tx working.
The start and stop frequencies can be programmed and chirp direction is programmable so callsign information can be encoded on to the transmission, probably with WSPR encoding method unless someone else has a better idea? I'm looking for an example of WSPR callsign decoder from received bits.
I'm currently looking at Pavel's adc_recorder_trigger example to figure out how to write data to memory!!

Tx Spectrum during tests