The previously mentioned adjustments to the FPGA code have been made and i now have 2 seconds' worth of samples in bram memory.
I can access this by mapping the memory in the C code on the ps, i then read alternate halves of the memory depending on the 'block' signal from the status register.
The FPGA appears to be writing to memory ok, and i can read it in the C code on the CPU, but when i stress the CPU at all the board does a hard reboot...... reason currently unknown!


11/2/2017
A fter a week of debugging the reboot problem turned out to be a power supply issue!
I had resorted to some other examples from Pavel's code and found the same problem with reboots.. this lead me to think it may not be my dodgy code!
The 2.5A 5v psu was replaced with a 1.5A one and now it works fine, the higher current one has a longer lead which is most likely the cause.
Anyway, now i can run the fpga and c code at the same time with about 20% cpu.
The FPGA writes samples to memory in 2 second cycles and resets at the 1pps input every 2 seconds, this is 160KB in total.
I then filter/decimate this by two and feed into the de-chirp code which outputs the time domain of the de-chirped signal across 5k points.
For now a simple pyhton script is used to plot an average of the data using matplotlib.

Here is a link to the FPGA Block Design from Vivado

Below is a screenshot of the signal in the time domain, the skirt of the peak is not bad seens as it is just coupling between the ports on the red pitaya! Weak reflected signals should easily be sharp enough to detect.
Whether this system works as well as using spectrumlab is yet to be tested - on the todo list.

Received Chirp