Returned to Red Pitaya Chirp Beacon project...

After a break from this project i have done a little more work with the Red Pitaya as my 6m Chirp Beacon Receiver, this is based around the sdr-receiver project of Pavel Demin.
The Chirp_freq_gen module i created drives a dds module then which drives the dac to generate the Tx signal, this appears to be functional with chirp direction for ID purposes. I'm still not sure what to use for the ID coding method.
The Tx config is controlled by the tx_cfg module via memory mapping via the linux ps.

The original 'sdr-receiver' Rx fpga code stores received 32bit samples in a 8k memory buffer, the ps code monitors the memory write pointer and grabs 4k chunks and send over tcp port when available.

The plan is to change this to write alternately to two blocks of memory capable of storing 1 second of samples at 10Ks/s, this will allow me to read back samples which are synchronised with the Tx/1pps clock input.
The CIC filters allow decimation by up to 6250, so 125000000/6250 = 20Ks/s output. This then feeds into the sinc correcting fir filter which decimates by two to give 10Ks/s to the ram writer module.
Currently the block ram writer just uses a counter which overflows at 1024 to address the memory in 64bit blocks (32bit I & 32bit Q) so 8192 Bytes of memory, but this is not synchronised.
My modification will just zero the counter at every two pps input cycles, a 1pps input and 1/2 pps output signal will be added to the ram writer block, the 1/2 pps signal will go to a status register that the ps will read to signal which block is being written to.
The bram module in the original design will be increased in size to allow for the larger amount of memory used which will now be 160KB, 20k deep and 64bit wide (2 seconds worth) and allocated as a 256K bock.
The bram is accessed by the ps by memory mapping to the pl ram reader module which uses 32bit wide blocks.

The basic chirp decoder is already written for the processing side, it appears to work fast enough on the pitaya cpu.

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